Display apparatus with data communication channel

ABSTRACT

Display apparatus comprises a connection for releasably connecting a display device (130;130&#39;) to the display apparatus. A data input (MON --  ID) receives first data from a first releasable connection (ST) to the display device (130;130&#39;) and for receiving second data from a second releasable connection (ID) to the display device (130;130&#39;). Switch (320) selectively connects the data input (MON --  ID) to either of the first releasable connection (ST) and the second releasable connection (ID). Display processor logic (310) is connected to the switch (320) for generating one or more video signals to generate an image on the display device (130,130&#39;) as a function of the data directed to the data input (MON --  ID) from the display device (130;130&#39;) by the switch (320). Because the data input is switchable between connection to first data and second data from the display device, the display apparatus can identify and subsequently control both display devices which identify themselves by providing fixed reference levels on one or more lines of the output port and display devices which identify themselves by providing display identification data in a serial bit stream along a data communication channel. The same physical connector can be used to attach both kinds of display device to the video processor logic.

BACKGROUND OF THE INVENTION

The present invention relates to display apparatus in which control datais communicated via a communication channel between a computer systemand a display device.

The control data includes parameters for specifying the geometry andresolution of an image presented on the display device. In a displayapparatus comprising a raster scanned display device such as for examplea cathode ray tube (CRT) display device, these parameters are determinedby the rates and durations of horizontal or line and vertical or framescan signals generated for producing the raster scan by electricalcircuits in the display device. To generate the image, the scan signalsare synchronized to video signals from a video adaptor in the computersystem by synchronization (sync) signals also generated by the videoadaptor.

Some display devices can only operate in a single display modecharacterized by a single set of parameters. Other display devices canbe configured to operate in any one of a number of different displaymodes each characterized by a different set of parameters. The latterwill hereinafter be referred to as multiple mode display devices.

Some recent display devices include display processor logic in the formof a microprocessor configured by computer program microcode to controlthe operation of the drive circuitry according to input line and framesync pulses from the host computer system and to image parametersettings manually input via a user control panel. The display processortypically comprises a serial data input. Image parameter datacorresponding to various different display modes is pre-loaded into thedisplay processor via the serial data input during initial set up andtesting of the display device.

In a display device controlled by a computer system it is desirable forthe computer system to identify the type of display device so thatappropriate video and sync signals can be generated. Many computersystems, such as the computer systems in the IBM PS/2 computer range forexample, include a video graphics adaptor having an output port forconnecting video and sync signals to the display device. The adaptoralso has logic responsive to the manner in which identification pins inthe output port are terminated when connected to the display device. Thelogic identifies the type of display device connected to the adaptorfrom these terminations.

UK Patent No. 2 162 026 describes an example of display apparatusemploying a multiple-mode display device receiving video and syncsignals from a computer system display adaptor. The display device canoperate in any one of four different display modes. The computer systemcan be instructed to provide sync pulses of either positive or negativepolarities. Each polarity combination indicates a different displaymode. The display device includes decoding logic for configuring thedisplay device to operate in a particular display mode in response topredetermined combinations of sync signal polarities and frequencies.

The conventional display apparatus hereinbefore described has theproblem that the interface between the display device and the computersystem can identify, and therefore generate appropriate controls signalsfor, only a limited number of different display devices. This limitationarises because of the number of pins available for device identificationand control is limited by the physical form of the output port.Typically, the output port is implemented by a 15 pin connector.

European Patent Application No. 0 456 923 describes display apparatuscomprising a display device for generating a visual output in responseto input data signals defining data to be displayed. A display adaptorcircuit generates the display data signals in a form specified bycontrol data identifying the display device. An output port transmitsthe data signals from the display adaptor circuit to the display deviceand transmits the control data from the display device to the displayadaptor circuit. A memory is located in the display device for storingthe control data in the form of a plurality of control codes.Communication logic communicates control codes between the memory andthe output port in response to a command signal from the display adaptorcircuit.

The display apparatus described in EP-A-0 456 923 solves the problem ofincreasing the number of different display devices which can beidentified and controlled by the computer system through theintroduction of a control data communication channel between a memory inthe display device and the video adaptor of the host computer system.The display adaptor in the computer system is adapted to receive displayidentification data from the display device via the communicationchannel. However, it is desirable for such a display adaptor to connectto not only to display devices in which provisions are made for the datacommunication channel and the storage of display identification data,but also to display devices in which no such provisions are made. Thereis hence an interest in providing both forwards and backwardscompatibility in display apparatus of the kind described in EP-A-O 456923.

SUMMARY OF THE INVENTION

In accordance with the present invention, there is now provided displayapparatus comprising: means for releasably connecting a display deviceto the display apparatus; a data input for receiving first data from afirst releasable connection to the display device and for receivingsecond data from a second releasable connection to the display device;switch means for selectively connecting the data input to either of thefirst releasable connection and the second releasable connection; anddisplay processor logic connected to the switch means for generating oneor more video signals to generate an image on the display device as afunction of the data directed to the data input from the display device,by the switch means.

Because the data input is switchable between connection to first datafrom the display device and second data from the display device, thedisplay apparatus of the present invention can identify and subsequentlycontrol both display devices which identify themselves by providingfixed reference on one or more lines of the output port and displaydevices which identify themselves by providing display identificationdata in a serial bit stream along a data communication channel. The samephysical connector can be used to attach both kinds of display device tothe video processor logic. The present invention therefore provides bothforwards and backwards compatibility in display apparatus of the kinddescribed in EP-A-0 456 923.

The switch means is preferably arranged to selectively connect the firstconnection to the display device to one of the data input and a controloutput for releasing the display device from a test mode of operation.This can prevent the display device from generating a test pattern suchas, for example, a full raster image once the display is connected tothe display apparatus of the present invention.

In a particularly preferred embodiment of the present invention, theswitch means comprises: a header having a plurality of electricallyconductive elements, the first connection, the second connection, thecontrol output, and the data input being connected to different ones ofthe elements; a first electrically conductive jumper connector forreleasably engaging different pairs of the conductive elements to linkthe data input to one of the first connection and the second connection;and a second electrically conductive jumper connector for releasablyengaging different pairs of the conductive elements to link the firstconnection to the control output when data input is linked by the firstjumper to the second connection.

It will be appreciated that the switch means may be implemented in anumber of ways. However, the header and jumper arrangement isparticularly preferred because it is relatively cheap and simple tointroduce in comparison with other switch technologies. The data inputcan be switched between the first and second connections simply bymoving the jumper from one pair of header to another.

It will be appreciated that the present invention extends to a computersystem comprising display apparatus of the kind described in thepreceding six paragraphs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computer system comprising displayapparatus of the present invention;

FIG. 2 is a block diagram of a display device for the computer system;

FIG. 3 is a block diagram of display apparatus of the present inventionin a first configuration;

FIG. 4 is a block diagram of display apparatus of the present inventionin a second configuration;

FIGS. 5A and 5B are plan views of first switch means for displayapparatus of the present invention; and

FIGS. 6A and 6B are plan views of second switch means for displayapparatus of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring first to FIG. 1, a computer system comprises a system unit 5including a random access memory (RAM) 10, a read only store (ROS) 20, acentral processing unit (CPU) 30, a communication adaptor 40, a displayadaptor 70, a pointing device adaptor 80, a keyboard adaptor 90, and amass storage device 100 as a hard disk drive or tape streamer forexample, all interconnected by a bus architecture 60. System unit 5 isconnected via adaptor 90 to a keyboard 110. A pointing device 120 suchas a touch screen, a tablet, or a mouse is connected to system unit 5via adaptor 80. System unit 5 is also connected via adaptor 70 and aninterface cable 135 to a display 130 such as a cathode ray tube (CRT)display or a liquid crystal display for example. A network 50 of othersystem units is connected to system unit 5 via communication adaptor 40.

In operation, CPU 30 processes data stored in a combination of RAM 10and mass storage device 100 under the control of computer program codestored in a combination of ROS 20, RAM 10, and mass storage device 100.Communication adaptor 40 controls transfer of data and computer programcode between system unit 5 and other system units in network 50 throughcommunication adaptor 40. Keyboard and mouse adaptors 90 and 80 permitdata and instructions to be manually entered into system unit 5 fromkeyboard 110 and pointing device 120 respectively. Display adaptor 70translates output data from system unit 5 into video signals, R, G andB, and horizontal and vertical picture synchronization (sync) signals, Hand V, for configuring display 130 to generate a visual data output. Busarchitecture 60 coordinates data transfer between RAM 10, ROS 20, CPU30, storage device 100, and adaptors 40, 90, 80 and 70.

Referring now to FIG. 2, display 130 comprises a display screen 210 inthe form of a color cathode ray display tube (CRT) connected to displaydrive circuitry 200. Display drive circuitry 200 comprises an Extra HighTension (EHT) generator 230 and a video amplifier 250 connected todisplay screen 210. Line and frame deflection coils 290 and 280 aredisposed around the neck of the CRT. Deflection coils 290 and 280 areconnected to line and frame scan circuits 220 and 240 respectively. Linescan circuit 220 and EHT generator 230 may each be in the form of aflyback circuit, the operation of which is well known by those skilledin the art. Furthermore, as is also well-known in the art, EHT generator230 and line scan circuit 220 may be integrated in a single flybackcircuit. A power supply (not shown) is connected via power supply rails(not shown) to EHT generator 230, video amplifier 250, and line andframe scan circuits 220 and 240. In use, the power supply provideselectrical power on the supply rails from Line and Neutral connections(not shown) to the domestic electricity mains supply. The power supplymay be in the form of a switch mode power supply, the operation of whichis well-understood by those skilled in the art.

EHT generator 230, video amplifier 250, and line and frame scan circuits220 and 240 are each connected to a display processor 270. Displayprocessor 270 comprises processor logic preferably in the form of amicrocomputer of the kind including microprocessor and accompanyingmemory. Drive circuitry 200 includes a user control panel 260 connectedto key-pad interrupt lines of display processor 270. Control panel 260comprises a plurality of manual operable switches.

In operation, EHT generator 230 generates an electric field within CRT210 for accelerating electrons in beams corresponding to the primarycolors of red, green and blue towards the screen of CRT. Line and framescan circuits 220 and 240 generate line and frame scan currents indeflection coils 290 and 280. The line and frame scan currents are inthe form of ramp signals to produce time-varying magnetic fields thatscan the electron beams across the screen of CRT 210 in a rasterpattern. The line and frame scan signals are synchronized by line andframe scan circuits to input line and frame synchronization (sync)signals H and V generated by video adaptor 70. Video amplifier 250modulates the red, green and blue electron beams to produce an outputdisplay on CRT 210 as a function of corresponding red, green and blueinput video signals R, G and B also generated by adaptor 70. Line andframe sync signals H and V and video signals R, G and B are supplied todisplay 130 from adaptor 70 along corresponding signal lines ininterface cable 135. The signal lines of interface cable 135 terminateat the end remote from display device 130 in a connector (not shown) fordetachably connecting the signal lines to adaptor 70. For compatibility,the connector is preferably a 15 pin D type connector although otherconnectors may be used.

Display processor 270 is configured to control the outputs of EHTgenerator 230, video amplifier 250, and line and frame scan circuits 220and 240 via control links 275 as functions of preprogrammed display modedata and inputs from user control 260. The display mode data includessets of preset image parameter values each corresponding to a differentpopular display mode such as, for example, 1024×768 pixels, 640×480pixels, or 1280×1024 pixels. Each set of image display parameter valuesincludes height and centering values for setting the output of framescan circuit 240; and width and centering values for controlling linescan circuit 220. In addition, the display mode data includes commonpreset image parameter values for controlling the gain and cutoff ofeach of the red, green and blue channels of video amplifier 250; andpreset control values for controlling the outputs of EHT generator 240.The image parameter values are selected by display processor 270 inresponse to input mode information from adaptor 70. The mode informationis delivered from adaptor 70 to display processor 270 via line and framesync lines H and V. Display processor 270 processes the selected imageparameter values to generate analog control levels on the control links.

A user may also manually adjust the control levels controlling red greenand blue video gains and cutoffs at video amplifier 250; and imagewidth, height, and centering at line and frame scan circuits 220 and 240via the user control panel 260. User control panel 260 includes a set ofup/down control keys for each of image height, centering, width,brightness and contrast. When, for example, the width up key isdepressed, user control panel 260 issues a interrupt to displayprocessor 270. The source of the interrupt is determined by displayprocessor 270 via an interrupt polling routine. In response to theinterrupt from the width key, display processor 270 progressivelyincreases the corresponding analog control level sent to line scancircuit 220. The width of the image progressively increases. When thedesired width is reached, the user releases the key. The removal of theinterrupt is detected by display processor 270, and the digital valuesetting the width control level is retained. The height, centering,brightness and contrast setting can be adjusted by the user in similarfashion. User control panel 260 further includes a store key. When theuser depresses the store key, an interrupt is produced to which displayprocessor 270 responds by storing in memory parameter valuescorresponding the current settings of the digital outputs to D to Aconvertor. The user can thus program into display 130 specific displayimage parameters according to personal preference.

Referring now to FIG. 3, interface cable 135 also includes a self testline ST. In accordance with the present invention, self test line ST isselectively connectable to a serial data input SD of display processor270 via switch means 330. During manufacture of display device 130, theaforementioned image parameter values may be pre-loaded into displayprocessor 270 via the serial data input and self test line ST. Displaydevice 130 also comprises a non-volatile memory 300 such as an EEPROM.The output RO of memory 300 is also selectively connectable to a selftest line ST of interface cable 135 via switch means 330. Switch means330 allows the self test line of interface cable 135 to be switchedbetween connection to the serial data input SD to display processor 270and the output of memory 300. In FIG. 3, switch means 330 is exemplifiedby a single pole double throw (SPDT) switch. Display adaptor 70comprises video processor logic detachably connected to the line sync H,the frame sync V, and the R, G and B video lines of interface cable 135via the aforementioned multi-pin connector (not shown). Video processorlogic 310 has a ground line OV and a display identification input MON₋₋ID. Input MON--ID is serial data input to video processor logic 310.Self test line ST of interface cable 135 is connectable, via switchmeans 320, to either ground line OV or input MON₋₋ ID to video processor310. Interface cable 135 further comprises a display identification lineID which is unused for signal transmission. Display identification lineID can be switched via switch means 320 between input MON₋₋ ID of videoprocessor logic 310 and an unconnected state denoted by N/C in FIG. 3.In FIG. 3, switch means 320 is exemplified by a double pole double throw(DPDT) switch.

Memory 300 contains a block of display identification data comprising ofthe order of 128 bytes of information fully describing the functionalcapabilities of display device 130. This data permits the computersystem to configure adaptor 70 to provide, via video processor logic310, the best possible signal match for the line and frame sync signalsH and V, and the video signals R, G, and B, between adaptor 70 anddisplay device 130. In operation, switch means 330 is normally set toconnect self test line ST of interface cable 135 to output RO of memory300. Switch means 320 in adaptor 70 is correspondingly set to connectself test line ST of interface cable 135 to the MON--ID input of videoprocessor logic 310, with line ID of interface cable 135 leftunconnected, at N/C, in adaptor 70. The display identification datastored in memory 300 can thus be serially read, one bit at a time, frommemory 300 into input MON₋₋ ID of video processor logic 310 via switchmeans 330, self test line ST, and switch means 320. The displayidentification data is preferably clocked into input MON₋₋ ID as afunction of the line sync signal H although it will be appreciated thatother system clocks may be used to effect reading of the contents ofmemory 300. The transmission of the display identification data frommemory 300 to video processor logic 310 is cyclic and continues as longas line sync signal H is present. After all the display identificationdata is read from memory 300 into video processor logic 310 at leastonce, ordering and interpretation of the display identification datawithin the computer system can be performed.

128 bytes of display identification data can thus be clocked from memory300 into video processor logic 310 along self test line ST in a minimumof 1024 cycles of line sync signal. The display identification data cantherefore by read in approximately two frame periods or around 30 ms.However, in multitasking computing applications, it is undesirable toinhibit interrupts of the computer system for 1024 or more cycles of theline sync signal. Furthermore, it is difficult to dynamicallyreconfigure adaptor 70 once operational. The display identification datais therefore read from display device 130 into adaptor 70 duringinitialization of the computer system. Initially, when the computersystem is turned on or "booted up", Power On Self Test (POST) code isexecuted by CPU 30 to test that the computer system is operational. Theinitialization process continues following execution of the POST codewith a device driver phase. In the device driver phase, device drivercode for each of the peripheral device adaptors 40, 70, 80 and 90 of thecomputer systems is retrieved from mass storage 100 and installed in RAM10 by CPU 30. The device driver code permits CPU 30 to control theperipheral device adaptors via bus architecture 60. The displayidentification data is read from memory 300 in display device 130 intovideo processor logic 310 of adaptor 70 during the device driver phaseso that the associated disabling of interrupts does not significantlyimpede the operation of the computer system. The display identificationdata is not read during the POST because display device 130 might not beswitched by then, in which case the display identification would not beavailable. Typically a significant period lapses between turn on and thebeginning of the device driver phase. The operator thus has time to turnon the display after turning on the computer system.

The device driver code for adaptor 70 uses Video Basic Input OutputSystem (VBIOS) code to read the display identification data bit by bitand to align the align the data read into bytes. Conventional devicedrivers rely on user intervention to set the resolution and line andrefresh rates (line and frame sync frequencies) for the display deviceattached. The user intervention is generally prompted by utilitiesprovided with the various adaptors available. These utilities vary inquality. The display identification data provided in accordance with thepresent invention gives the device driver all the information generallyrequired by the utilities, together with additional information that theuser may not have to hand, to allow the computer system to select themost appropriate fonts or refresh rates, for example. This permits theuser to optimize the performance of the computer system.

During manufacturing or field servicing for example, switch means 330can be set to connect self test line ST of interface cable 135 to inputSD display processor 270 instead of to output RO of memory 300. Testdata can then be serially loaded into display processor 270 from asuitable test station on the production line to test display device 130prior to shipment. The aforementioned preset image parameter valuesforming the display mode data used in display processor 270 can also beloaded into display processor 270 in this manner.

In some circumstances, it may be desirable to use adaptor 70 to driveconventional display devices that do not have the ability to providedisplay information (ie: do not have memory 300). A typical example ofsuch a conventional display device is able to present a four bitidentification code to a display adaptor of a computer system via fourID bit lines included in its interface cable. This conventional displaydevice also generates a test raster image when the self test line of itsinterface cable is not grounded by the computer system. Referring now toFIG. 4, compatibility with a conventional display device 130' of thiskind just described is achieved in accordance with the present inventionthrough switch means 320. Switch means 320 can be set to connect selftest line ST to system ground 0V instead of to data input MON₋₋ ID andto connect ID line to data input MON₋₋ ID instead of leaving itunconnected. When switch means 320 is set to connect self test line STto system ground 0V and conventional display device 130' is attached toadaptor 70, the test raster generator of the conventional display device130' is disabled. However, adaptor 70 can still identify conventionaldisplay device 130' because the ID line of its interface cable nowconnected to the data input MON₋₋ ID of video processor logic 310 viaswitch means 320. Adaptor 70 therefore provides backwards compatibilitywith conventional displays as well as forwards compatibility withdisplays able to provide display identification data.

In the embodiments of the present invention depicted in FIGS. 3 and 4,switch means 320 and 330 are implemented by DPDT and SPDT switchesrespectively. However, it will be appreciated that in other embodimentsof the present invention, switch means 320 and 330 may be implementedusing other techniques. For example, in other embodiments of the presentinvention, switch means 320 and 330 may each be implementedelectronically by multiplexer logic or the like.

Referring now to FIGS. 5A and 5B, in particularly preferred embodimentsof the present invention, switch means 330 is implemented by printedcircuit board mounted 3 pin header 410 and a pluggable jumper connector400 for connecting adjacent pairs of the pins of header 400. The pins ofheader 400 are connected to self test line ST of interface cable 135,serial data input SD to display processor 270 and output RO of memory300, respectively. Jumper 400 can be manually plugged to connect selftest line ST to either serial input SD as shown in FIG. 5A or to memoryoutput RO as shown in FIG. 5B. Referring now to FIGS. 6A and 6B, inparticularly preferred embodiments of the present invention, switchmeans 320 is implemented by printed circuit board mounted 4 pin header520 and pluggable jumper connectors 500 and 510 for connecting adjacentpairs of the pins of header 500. The pins of header 520 are connected tosystem ground OV of video processor logic 310, self test line ST ofinterface cable 135, serial input MON₋₋ ID to video processor logic 310,and identification line ID of interface cable 135. With reference toFIG. 6A, to configure adaptor 70 for connection to display device 130having memory 300, jumper 500 is plugged into header 520 to connect selftest line ST to data input MON₋₋ ID. Referring to FIG. 6B, to configureadaptor 70 for connection to a conventional display device, jumper 500is plugged into header 520 to connect self test line ST to system groundOV and additional jumper 510 is plugged into header to link data inputMON₋₋ ID to identification line ID.

The implementations of switch means 330 and 320 described above withreference to FIG. 4 and 5 are particularly attractive by reason of theirsimplicity relative to other technologies such as electronicmultiplexers or other mechanical multi-pole switches.

Embodiments of the present invention have been hereinbefore describedwith reference to a color CRT display device. However, it will beappreciated that the present invention is equally applicable to displayapparatus comprising other forms of display screens such as, forexample, monochrome CRTs, or liquid crystal display panels and the like.

We claim:
 1. Display apparatus, comprising:a connector for connecting adisplay device (130;130') to the display apparatus; a data input (MON₋₋ID) for receiving first data, in serial data bit stream format, from afirst output (ST) of the display device (130;130') and for receivingsecond data from a second output (ID) of the display device (130;130');switch means (320) for selectively connecting the data input (MON₋₋ ID)to either of the first output (ST) or the second output (ID); anddisplay processor logic (310) connected to the switch means (320) forgenerating one or more video signals to generate an image on the displaydevice (130,130') as a function of the data directed to the data input(MON₋₋ ID) by the switch means (320).
 2. Apparatus as claimed in claim1, wherein the second data is in the form of a reference level. 3.Apparatus as claimed in any preceding claim, wherein the switch means(320) is arranged to selectively connect the first output (ST) to thedisplay device (130;130') to one of the data input (MON₋₋ ID) and acontrol output (0V) for releasing the display device (130;130') from atest mode of operation.
 4. Apparatus as claimed in claim 3, wherein theswitch means (320) comprises: a header (520) having a plurality ofelectrically conductive elements, the first output (ST), the secondoutput (ID), the control output (0V), and the data input (MON₋₋ ID)being connected to different ones of the elements; a first electricallyconductive jumper connector (500) for releasably engaging differentpairs of the conductive elements to link the data input (MON₋₋ ID) toone of the first output (ST) and the second output (ID); and a secondelectrically conductive jumper connector (510) for releasably engagingdifferent pairs of the conductive elements to link the first output (ST)to the control output (0V) when data input (MON₋₋ ID) is linked by thefirst jumper (500) to the second output (ID).
 5. A computer system,comprising:a processing unit (30); a display adapter (70) connected andresponsive to the processing unit (30); a connector for connecting adisplay device (130;130') to the display adapter (70); a data input(MON₋₋ ID) for receiving first data, in serial data bit stream format,from a first output (ST) of the display device (130;130') and forreceiving second data from a second output (ID) of the display device(130;130'); switch means (320) for selectively connecting the data input(MON₋₋) to either of the first output (ST) or the second output (ID);and display processor logic (310) connected to the switch means (320)for generating one or more video signals to generate an image on thedisplay device (130;130') as a function of the data directed to the datainput (MON₋₋) by the switch means (320).